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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#typedef-members">Typedefs</a> &#124;
<a href="#var-members">Variables</a>  </div>
  <div class="headertitle">
<div class="title">Macros<div class="ingroups"><a class="el" href="group__group__syslib.html">SysLib       (System Library)</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
API Reference</h2></td></tr>
<tr class="memitem:group__group__syslib__macros__status__codes"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__status__codes.html">Status codes</a></td></tr>
<tr class="memdesc:group__group__syslib__macros__status__codes"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function status type codes. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__syslib__macros__assert"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__assert.html">Assert Classes and Levels</a></td></tr>
<tr class="memdesc:group__group__syslib__macros__assert"><td class="mdescLeft">&#160;</td><td class="mdescRight">Defines for the Assert Classes and Levels. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__syslib__macros__reset__cause"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html">Reset cause</a></td></tr>
<tr class="memdesc:group__group__syslib__macros__reset__cause"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define RESET_CAUSE mask values. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__syslib__macros__unique__id"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__unique__id.html">Unique ID</a></td></tr>
<tr class="memdesc:group__group__syslib__macros__unique__id"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unique ID fields positions. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga7df4bf9c8ea1a114369c852889496aae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga7df4bf9c8ea1a114369c852889496aae">CY_CPU_CORTEX_M0P</a>&#160;&#160;&#160;(__CORTEX_M == 0U)</td></tr>
<tr class="memdesc:ga7df4bf9c8ea1a114369c852889496aae"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro for ARM CORTEX CM0P.  <a href="#ga7df4bf9c8ea1a114369c852889496aae">More...</a><br /></td></tr>
<tr class="separator:ga7df4bf9c8ea1a114369c852889496aae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafed84424a1f1d7d64613d79689a3ee23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gafed84424a1f1d7d64613d79689a3ee23">CY_CPU_CORTEX_M4</a>&#160;&#160;&#160;(__CORTEX_M == 4U)</td></tr>
<tr class="memdesc:gafed84424a1f1d7d64613d79689a3ee23"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro for ARM CORTEX CM4.  <a href="#gafed84424a1f1d7d64613d79689a3ee23">More...</a><br /></td></tr>
<tr class="separator:gafed84424a1f1d7d64613d79689a3ee23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga724e1d0e20719c6ecc0fcc30a54acd96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga724e1d0e20719c6ecc0fcc30a54acd96">CY_CPU_CORTEX_M7</a>&#160;&#160;&#160;(__CORTEX_M == 7U)</td></tr>
<tr class="memdesc:ga724e1d0e20719c6ecc0fcc30a54acd96"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro for ARM CORTEX CM7.  <a href="#ga724e1d0e20719c6ecc0fcc30a54acd96">More...</a><br /></td></tr>
<tr class="separator:ga724e1d0e20719c6ecc0fcc30a54acd96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf603dd63838423fbc41f4d27f269839d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaf603dd63838423fbc41f4d27f269839d">CY_CPU_CORTEX_M55</a>&#160;&#160;&#160;(__CORTEX_M == 55U)</td></tr>
<tr class="memdesc:gaf603dd63838423fbc41f4d27f269839d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro for ARM CORTEX CM55.  <a href="#gaf603dd63838423fbc41f4d27f269839d">More...</a><br /></td></tr>
<tr class="separator:gaf603dd63838423fbc41f4d27f269839d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6ac26e754ab934c0f6218a85dc7ef2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gac6ac26e754ab934c0f6218a85dc7ef2f">CY_CPU_CORTEX_M33</a>&#160;&#160;&#160;(__CORTEX_M == 33U)</td></tr>
<tr class="memdesc:gac6ac26e754ab934c0f6218a85dc7ef2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro for ARM CORTEX CM33.  <a href="#gac6ac26e754ab934c0f6218a85dc7ef2f">More...</a><br /></td></tr>
<tr class="separator:gac6ac26e754ab934c0f6218a85dc7ef2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85e9d9dff858ec3d8dc503e008d73ee9"><td class="memItemLeft" align="right" valign="top"><a id="ga85e9d9dff858ec3d8dc503e008d73ee9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga85e9d9dff858ec3d8dc503e008d73ee9">CY_ARM_FAULT_DEBUG_ENABLED</a>&#160;&#160;&#160;(1U)</td></tr>
<tr class="memdesc:ga85e9d9dff858ec3d8dc503e008d73ee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro to enable the Fault Handler. <br /></td></tr>
<tr class="separator:ga85e9d9dff858ec3d8dc503e008d73ee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c0ebfbdb81ba7c5a3601a4b274b7666"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga1c0ebfbdb81ba7c5a3601a4b274b7666">CY_ARM_FAULT_DEBUG</a>&#160;&#160;&#160;(<a class="el" href="group__group__syslib__macros.html#ga85e9d9dff858ec3d8dc503e008d73ee9">CY_ARM_FAULT_DEBUG_ENABLED</a>)</td></tr>
<tr class="memdesc:ga1c0ebfbdb81ba7c5a3601a4b274b7666"><td class="mdescLeft">&#160;</td><td class="mdescRight">The macro defines if the Fault Handler is enabled.  <a href="#ga1c0ebfbdb81ba7c5a3601a4b274b7666">More...</a><br /></td></tr>
<tr class="separator:ga1c0ebfbdb81ba7c5a3601a4b274b7666"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga42db4418238e39bcfd002d19df2587f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga42db4418238e39bcfd002d19df2587f5">CY_SYSLIB_DELAY_CALIBRATION_FACTOR</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:ga42db4418238e39bcfd002d19df2587f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is to be enabled and set appropriately for the CPU's which has branch prediction enabled, so the delay can work accurately.  <a href="#ga42db4418238e39bcfd002d19df2587f5">More...</a><br /></td></tr>
<tr class="separator:ga42db4418238e39bcfd002d19df2587f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf65a7f5b872c3af67a2a4214ed06608"><td class="memItemLeft" align="right" valign="top"><a id="gaaf65a7f5b872c3af67a2a4214ed06608"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaaf65a7f5b872c3af67a2a4214ed06608">CY_SYSLIB_DRV_VERSION_MAJOR</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaaf65a7f5b872c3af67a2a4214ed06608"><td class="mdescLeft">&#160;</td><td class="mdescRight">The driver major version. <br /></td></tr>
<tr class="separator:gaaf65a7f5b872c3af67a2a4214ed06608"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12200ca1ff7e119d8fe12f70d525651a"><td class="memItemLeft" align="right" valign="top"><a id="ga12200ca1ff7e119d8fe12f70d525651a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga12200ca1ff7e119d8fe12f70d525651a">CY_SYSLIB_DRV_VERSION_MINOR</a>&#160;&#160;&#160;80</td></tr>
<tr class="memdesc:ga12200ca1ff7e119d8fe12f70d525651a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The driver minor version. <br /></td></tr>
<tr class="separator:ga12200ca1ff7e119d8fe12f70d525651a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36d87757b3a3e0fa1dd2501e17296927"><td class="memItemLeft" align="right" valign="top"><a id="ga36d87757b3a3e0fa1dd2501e17296927"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga36d87757b3a3e0fa1dd2501e17296927">CY_SECTION_RAMFUNC_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_ramfunc&quot;)</td></tr>
<tr class="memdesc:ga36d87757b3a3e0fa1dd2501e17296927"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of the function placed to the SRAM area by the linker. <br /></td></tr>
<tr class="separator:ga36d87757b3a3e0fa1dd2501e17296927"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1586b89384bdb74bce9b98f570f1c5c"><td class="memItemLeft" align="right" valign="top"><a id="gae1586b89384bdb74bce9b98f570f1c5c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gae1586b89384bdb74bce9b98f570f1c5c">CY_SECTION_RAMFUNC_END</a></td></tr>
<tr class="memdesc:gae1586b89384bdb74bce9b98f570f1c5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the function placed to the SRAM area by the linker. <br /></td></tr>
<tr class="separator:gae1586b89384bdb74bce9b98f570f1c5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaebaccd68a36953a6eb41f17bf1165d9"><td class="memItemLeft" align="right" valign="top"><a id="gaaebaccd68a36953a6eb41f17bf1165d9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaaebaccd68a36953a6eb41f17bf1165d9">CY_SECTION_SRAM1_CODE_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sram1_code&quot;)</td></tr>
<tr class="memdesc:gaaebaccd68a36953a6eb41f17bf1165d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:gaaebaccd68a36953a6eb41f17bf1165d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ab2f8e0020b330ed3aaa73ab58478e8"><td class="memItemLeft" align="right" valign="top"><a id="ga5ab2f8e0020b330ed3aaa73ab58478e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga5ab2f8e0020b330ed3aaa73ab58478e8">CY_SECTION_SRAM1_CODE_END</a></td></tr>
<tr class="memdesc:ga5ab2f8e0020b330ed3aaa73ab58478e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:ga5ab2f8e0020b330ed3aaa73ab58478e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c5f42835a7a27f2bb7b71488878fbb6"><td class="memItemLeft" align="right" valign="top"><a id="ga3c5f42835a7a27f2bb7b71488878fbb6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga3c5f42835a7a27f2bb7b71488878fbb6">CY_SECTION_SRAM1_DATANS_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sram1_data_ns&quot;)</td></tr>
<tr class="memdesc:ga3c5f42835a7a27f2bb7b71488878fbb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:ga3c5f42835a7a27f2bb7b71488878fbb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga714568593106feb85cbf2c97370bb09b"><td class="memItemLeft" align="right" valign="top"><a id="ga714568593106feb85cbf2c97370bb09b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga714568593106feb85cbf2c97370bb09b">CY_SECTION_SRAM1_DATANS_END</a></td></tr>
<tr class="memdesc:ga714568593106feb85cbf2c97370bb09b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:ga714568593106feb85cbf2c97370bb09b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad32952797b18dd15921e1f4c04cb5ace"><td class="memItemLeft" align="right" valign="top"><a id="gad32952797b18dd15921e1f4c04cb5ace"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gad32952797b18dd15921e1f4c04cb5ace">CY_SECTION_SRAM0_DATANS_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sram0_data_ns&quot;)</td></tr>
<tr class="memdesc:gad32952797b18dd15921e1f4c04cb5ace"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:gad32952797b18dd15921e1f4c04cb5ace"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae86c476f330a129b1a30fc84062bd83b"><td class="memItemLeft" align="right" valign="top"><a id="gae86c476f330a129b1a30fc84062bd83b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gae86c476f330a129b1a30fc84062bd83b">CY_SECTION_SRAM0_DATANS_END</a></td></tr>
<tr class="memdesc:gae86c476f330a129b1a30fc84062bd83b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the function placed to the SRAM1 area by the linker. <br /></td></tr>
<tr class="separator:gae86c476f330a129b1a30fc84062bd83b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05d6029120643ca76b079fdf2fd1ea12"><td class="memItemLeft" align="right" valign="top"><a id="ga05d6029120643ca76b079fdf2fd1ea12"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga05d6029120643ca76b079fdf2fd1ea12">CY_SECTION_INIT_CODECOPY_BEGIN</a></td></tr>
<tr class="memdesc:ga05d6029120643ca76b079fdf2fd1ea12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of the code block to be copied to SRAM by the linker during init. <br /></td></tr>
<tr class="separator:ga05d6029120643ca76b079fdf2fd1ea12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10926a1e1ebe0e4c7b2024a80cf93266"><td class="memItemLeft" align="right" valign="top"><a id="ga10926a1e1ebe0e4c7b2024a80cf93266"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga10926a1e1ebe0e4c7b2024a80cf93266">CY_SECTION_INIT_CODECOPY_END</a></td></tr>
<tr class="memdesc:ga10926a1e1ebe0e4c7b2024a80cf93266"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the code block to be copied to SRAM by the linker during init. <br /></td></tr>
<tr class="separator:ga10926a1e1ebe0e4c7b2024a80cf93266"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b993962501511509b8b00983f63a3db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga2b993962501511509b8b00983f63a3db">CY_SECTION_SHAREDMEM</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sharedmem&quot;)</td></tr>
<tr class="memdesc:ga2b993962501511509b8b00983f63a3db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define variable to be placed to the shared SRAM area by the linker.  <a href="#ga2b993962501511509b8b00983f63a3db">More...</a><br /></td></tr>
<tr class="separator:ga2b993962501511509b8b00983f63a3db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffa03f0f4964652cf1e8981829e56214"><td class="memItemLeft" align="right" valign="top"><a id="gaffa03f0f4964652cf1e8981829e56214"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaffa03f0f4964652cf1e8981829e56214">CY_SECTION_SHAREDMEM_SEC</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sharedmem_sec&quot;)</td></tr>
<tr class="memdesc:gaffa03f0f4964652cf1e8981829e56214"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define variable to be placed to the secured shared SRAM area by the linker. <br /></td></tr>
<tr class="separator:gaffa03f0f4964652cf1e8981829e56214"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ee9ec1a465f6c127790e0077a5bdc27"><td class="memItemLeft" align="right" valign="top"><a id="ga1ee9ec1a465f6c127790e0077a5bdc27"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga1ee9ec1a465f6c127790e0077a5bdc27">CY_SECTION_SOCMEMSRAMCODE_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_socmem_code&quot;)</td></tr>
<tr class="memdesc:ga1ee9ec1a465f6c127790e0077a5bdc27"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define start of code to be placed to the SOCMEMSRAM area by the linker. <br /></td></tr>
<tr class="separator:ga1ee9ec1a465f6c127790e0077a5bdc27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1587da210f7941e4b2fa119aa760d39b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga1587da210f7941e4b2fa119aa760d39b">CY_SECTION_SOCMEMSRAMDATA_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_socmem_data&quot;)</td></tr>
<tr class="memdesc:ga1587da210f7941e4b2fa119aa760d39b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of code placed to the SOCMEMSRAM area by the linker.  <a href="#ga1587da210f7941e4b2fa119aa760d39b">More...</a><br /></td></tr>
<tr class="separator:ga1587da210f7941e4b2fa119aa760d39b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa768a043f67cc8909f97862a2b221813"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaa768a043f67cc8909f97862a2b221813">CY_SECTION_SOCMEMSRAMSHARED_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_shared_socmem&quot;)</td></tr>
<tr class="memdesc:gaa768a043f67cc8909f97862a2b221813"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of code placed to the SOCMEMSRAM area by the linker.  <a href="#gaa768a043f67cc8909f97862a2b221813">More...</a><br /></td></tr>
<tr class="separator:gaa768a043f67cc8909f97862a2b221813"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4b6fb05dfeabea3867f3de020c7f2b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gac4b6fb05dfeabea3867f3de020c7f2b4">CY_SECTION_SRAM0DATA_BEGIN</a>&#160;&#160;&#160;CY_SECTION(&quot;.cy_sram0_data&quot;)</td></tr>
<tr class="memdesc:gac4b6fb05dfeabea3867f3de020c7f2b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of shared data to be placed to the SOCMEMSRAM area by the linker.  <a href="#gac4b6fb05dfeabea3867f3de020c7f2b4">More...</a><br /></td></tr>
<tr class="separator:gac4b6fb05dfeabea3867f3de020c7f2b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac60723c3b363d2a66e6351fa46750c74"><td class="memItemLeft" align="right" valign="top"><a id="gac60723c3b363d2a66e6351fa46750c74"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gac60723c3b363d2a66e6351fa46750c74">CY_SECTION_SRAM0DATA_END</a></td></tr>
<tr class="memdesc:gac60723c3b363d2a66e6351fa46750c74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Define end of the function placed to the ITCM area by the linker. <br /></td></tr>
<tr class="separator:gac60723c3b363d2a66e6351fa46750c74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae55b339d6807f66fad9f51d463d44b0b"><td class="memItemLeft" align="right" valign="top"><a id="gae55b339d6807f66fad9f51d463d44b0b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gae55b339d6807f66fad9f51d463d44b0b">CY_MAX_FILE_NAME_SIZE</a>&#160;&#160;&#160;(24U)</td></tr>
<tr class="memdesc:gae55b339d6807f66fad9f51d463d44b0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The max size of the file name which stores the ASSERT location. <br /></td></tr>
<tr class="separator:gae55b339d6807f66fad9f51d463d44b0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae43177fc1f4a6fcb65e3893ff492ae44"><td class="memItemLeft" align="right" valign="top"><a id="gae43177fc1f4a6fcb65e3893ff492ae44"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gae43177fc1f4a6fcb65e3893ff492ae44">CY_R0_Pos</a>&#160;&#160;&#160;(0U)</td></tr>
<tr class="memdesc:gae43177fc1f4a6fcb65e3893ff492ae44"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the R0 content in a fault structure. <br /></td></tr>
<tr class="separator:gae43177fc1f4a6fcb65e3893ff492ae44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c9c49ab9747ac458f2cc19cd8e8e0b8"><td class="memItemLeft" align="right" valign="top"><a id="ga2c9c49ab9747ac458f2cc19cd8e8e0b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga2c9c49ab9747ac458f2cc19cd8e8e0b8">CY_R1_Pos</a>&#160;&#160;&#160;(1U)</td></tr>
<tr class="memdesc:ga2c9c49ab9747ac458f2cc19cd8e8e0b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the R1 content in a fault structure. <br /></td></tr>
<tr class="separator:ga2c9c49ab9747ac458f2cc19cd8e8e0b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa74b12b7661cea3b360e7644000cff36"><td class="memItemLeft" align="right" valign="top"><a id="gaa74b12b7661cea3b360e7644000cff36"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaa74b12b7661cea3b360e7644000cff36">CY_R2_Pos</a>&#160;&#160;&#160;(2U)</td></tr>
<tr class="memdesc:gaa74b12b7661cea3b360e7644000cff36"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the R2 content in a fault structure. <br /></td></tr>
<tr class="separator:gaa74b12b7661cea3b360e7644000cff36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga965a1ac3e7ec8d3252c6fde108007c93"><td class="memItemLeft" align="right" valign="top"><a id="ga965a1ac3e7ec8d3252c6fde108007c93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga965a1ac3e7ec8d3252c6fde108007c93">CY_R3_Pos</a>&#160;&#160;&#160;(3U)</td></tr>
<tr class="memdesc:ga965a1ac3e7ec8d3252c6fde108007c93"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the R3 content in a fault structure. <br /></td></tr>
<tr class="separator:ga965a1ac3e7ec8d3252c6fde108007c93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31eef2178fe02acd8cc183f878cc8e10"><td class="memItemLeft" align="right" valign="top"><a id="ga31eef2178fe02acd8cc183f878cc8e10"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga31eef2178fe02acd8cc183f878cc8e10">CY_R12_Pos</a>&#160;&#160;&#160;(4U)</td></tr>
<tr class="memdesc:ga31eef2178fe02acd8cc183f878cc8e10"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the R12 content in a fault structure. <br /></td></tr>
<tr class="separator:ga31eef2178fe02acd8cc183f878cc8e10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67889b7144b97fff4a946c1db8b427fd"><td class="memItemLeft" align="right" valign="top"><a id="ga67889b7144b97fff4a946c1db8b427fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga67889b7144b97fff4a946c1db8b427fd">CY_LR_Pos</a>&#160;&#160;&#160;(5U)</td></tr>
<tr class="memdesc:ga67889b7144b97fff4a946c1db8b427fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the LR content in a fault structure. <br /></td></tr>
<tr class="separator:ga67889b7144b97fff4a946c1db8b427fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac80e133f34a5d1ee87655ce0addbc852"><td class="memItemLeft" align="right" valign="top"><a id="gac80e133f34a5d1ee87655ce0addbc852"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gac80e133f34a5d1ee87655ce0addbc852">CY_PC_Pos</a>&#160;&#160;&#160;(6U)</td></tr>
<tr class="memdesc:gac80e133f34a5d1ee87655ce0addbc852"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the PC content in a fault structure. <br /></td></tr>
<tr class="separator:gac80e133f34a5d1ee87655ce0addbc852"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad891a1aaa3452efd86d0167738c2ae4a"><td class="memItemLeft" align="right" valign="top"><a id="gad891a1aaa3452efd86d0167738c2ae4a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gad891a1aaa3452efd86d0167738c2ae4a">CY_PSR_Pos</a>&#160;&#160;&#160;(7U)</td></tr>
<tr class="memdesc:gad891a1aaa3452efd86d0167738c2ae4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The position of the PSR content in a fault structure. <br /></td></tr>
<tr class="separator:gad891a1aaa3452efd86d0167738c2ae4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga340c178dff79aaf98298cb40037cf808"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga340c178dff79aaf98298cb40037cf808">CY_UNUSED_PARAM</a>(a)&#160;&#160;&#160;(void)(a)</td></tr>
<tr class="memdesc:ga340c178dff79aaf98298cb40037cf808"><td class="mdescLeft">&#160;</td><td class="mdescRight">Suppresses the unused parameter warning.  <a href="#ga340c178dff79aaf98298cb40037cf808">More...</a><br /></td></tr>
<tr class="separator:ga340c178dff79aaf98298cb40037cf808"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f6cdb90cc67d703db8007cd2b87633a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga5f6cdb90cc67d703db8007cd2b87633a">CY_ARRAY_SIZE</a>(x)&#160;&#160;&#160;(sizeof(x) / sizeof((x)[0]))</td></tr>
<tr class="memdesc:ga5f6cdb90cc67d703db8007cd2b87633a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the size of Array.  <a href="#ga5f6cdb90cc67d703db8007cd2b87633a">More...</a><br /></td></tr>
<tr class="separator:ga5f6cdb90cc67d703db8007cd2b87633a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16efc8820d2ece85d8dee3aed3198b6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga16efc8820d2ece85d8dee3aed3198b6f">CY_IPC_DATA_FOR_CM4_SOFT_RESET</a>&#160;&#160;&#160;(0x1B000002UL)</td></tr>
<tr class="memdesc:ga16efc8820d2ece85d8dee3aed3198b6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit[31:24] Opcode = 0x1B (SoftReset) Bit[7:1] Type = 1 (Only CM4 reset)  <a href="#ga16efc8820d2ece85d8dee3aed3198b6f">More...</a><br /></td></tr>
<tr class="separator:ga16efc8820d2ece85d8dee3aed3198b6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gadbea1421faf52e66ab5190e91b2fca74"><td class="memItemLeft" align="right" valign="top"><a id="gadbea1421faf52e66ab5190e91b2fca74"></a>
typedef EFUSE_Type&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gadbea1421faf52e66ab5190e91b2fca74">cy_syslib_lcs_data_t</a></td></tr>
<tr class="memdesc:gadbea1421faf52e66ab5190e91b2fca74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of block with LCS data. <br /></td></tr>
<tr class="separator:gadbea1421faf52e66ab5190e91b2fca74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71c09beda7671d1f69c8f06a546e2ae6"><td class="memItemLeft" align="right" valign="top"><a id="ga71c09beda7671d1f69c8f06a546e2ae6"></a>
typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga71c09beda7671d1f69c8f06a546e2ae6">cy_israddress</a>) (void)</td></tr>
<tr class="memdesc:ga71c09beda7671d1f69c8f06a546e2ae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of ISR callbacks. <br /></td></tr>
<tr class="separator:ga71c09beda7671d1f69c8f06a546e2ae6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40bb5262bf908c328fbcfbe5d29d0201"><td class="memItemLeft" align="right" valign="top"><a id="ga40bb5262bf908c328fbcfbe5d29d0201"></a>
typedef char&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga40bb5262bf908c328fbcfbe5d29d0201">char_t</a></td></tr>
<tr class="memdesc:ga40bb5262bf908c328fbcfbe5d29d0201"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specific-length typedef for the basic numerical types of char. <br /></td></tr>
<tr class="separator:ga40bb5262bf908c328fbcfbe5d29d0201"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4611b605e45ab401f02cab15c5e38715"><td class="memItemLeft" align="right" valign="top"><a id="ga4611b605e45ab401f02cab15c5e38715"></a>
typedef float&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga4611b605e45ab401f02cab15c5e38715">float32_t</a></td></tr>
<tr class="memdesc:ga4611b605e45ab401f02cab15c5e38715"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specific-length typedef for the basic numerical types of float. <br /></td></tr>
<tr class="separator:ga4611b605e45ab401f02cab15c5e38715"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac55f3ae81b5bc9053760baacf57e47f4"><td class="memItemLeft" align="right" valign="top"><a id="gac55f3ae81b5bc9053760baacf57e47f4"></a>
typedef double&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gac55f3ae81b5bc9053760baacf57e47f4">float64_t</a></td></tr>
<tr class="memdesc:gac55f3ae81b5bc9053760baacf57e47f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specific-length typedef for the basic numerical types of double. <br /></td></tr>
<tr class="separator:gac55f3ae81b5bc9053760baacf57e47f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:ga7282e29cd9742f5db2014a09da1c0e93"><td class="memItemLeft" align="right" valign="top"><a id="ga7282e29cd9742f5db2014a09da1c0e93"></a>
<a class="el" href="group__group__syslib__macros.html#ga40bb5262bf908c328fbcfbe5d29d0201">char_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga7282e29cd9742f5db2014a09da1c0e93">cy_assertFileName</a> [<a class="el" href="group__group__syslib__macros.html#gae55b339d6807f66fad9f51d463d44b0b">CY_MAX_FILE_NAME_SIZE</a>+1]</td></tr>
<tr class="memdesc:ga7282e29cd9742f5db2014a09da1c0e93"><td class="mdescLeft">&#160;</td><td class="mdescRight">The assert buffer. <br /></td></tr>
<tr class="separator:ga7282e29cd9742f5db2014a09da1c0e93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ca8a8fef36a5ee4effb121ad7dd12ba"><td class="memItemLeft" align="right" valign="top"><a id="ga8ca8a8fef36a5ee4effb121ad7dd12ba"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#ga8ca8a8fef36a5ee4effb121ad7dd12ba">cy_assertLine</a></td></tr>
<tr class="memdesc:ga8ca8a8fef36a5ee4effb121ad7dd12ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">The assert line value. <br /></td></tr>
<tr class="separator:ga8ca8a8fef36a5ee4effb121ad7dd12ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7dba06c278f198fd2322d855eaaf54a"><td class="memItemLeft" align="right" valign="top"><a id="gaa7dba06c278f198fd2322d855eaaf54a"></a>
<a class="el" href="structcy__stc__fault__frame__t.html">cy_stc_fault_frame_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros.html#gaa7dba06c278f198fd2322d855eaaf54a">cy_faultFrame</a></td></tr>
<tr class="memdesc:gaa7dba06c278f198fd2322d855eaaf54a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fault frame structure. <br /></td></tr>
<tr class="separator:gaa7dba06c278f198fd2322d855eaaf54a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga7df4bf9c8ea1a114369c852889496aae"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7df4bf9c8ea1a114369c852889496aae">&#9670;&nbsp;</a></span>CY_CPU_CORTEX_M0P</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define CY_CPU_CORTEX_M0P&#160;&#160;&#160;(__CORTEX_M == 0U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The macro for ARM CORTEX CM0P. </p>
<p>CM0+ core CPU Code </p>

</div>
</div>
<a id="gafed84424a1f1d7d64613d79689a3ee23"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafed84424a1f1d7d64613d79689a3ee23">&#9670;&nbsp;</a></span>CY_CPU_CORTEX_M4</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define CY_CPU_CORTEX_M4&#160;&#160;&#160;(__CORTEX_M == 4U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The macro for ARM CORTEX CM4. </p>
<p>CM4 core CPU Code </p>

</div>
</div>
<a id="ga724e1d0e20719c6ecc0fcc30a54acd96"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga724e1d0e20719c6ecc0fcc30a54acd96">&#9670;&nbsp;</a></span>CY_CPU_CORTEX_M7</h2>

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      <table class="memname">
        <tr>
          <td class="memname">#define CY_CPU_CORTEX_M7&#160;&#160;&#160;(__CORTEX_M == 7U)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The macro for ARM CORTEX CM7. </p>
<p>CM7 core CPU Code </p>

</div>
</div>
<a id="gaf603dd63838423fbc41f4d27f269839d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf603dd63838423fbc41f4d27f269839d">&#9670;&nbsp;</a></span>CY_CPU_CORTEX_M55</h2>

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          <td class="memname">#define CY_CPU_CORTEX_M55&#160;&#160;&#160;(__CORTEX_M == 55U)</td>
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<p>The macro for ARM CORTEX CM55. </p>
<p>CM55 core CPU Code </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac6ac26e754ab934c0f6218a85dc7ef2f">&#9670;&nbsp;</a></span>CY_CPU_CORTEX_M33</h2>

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          <td class="memname">#define CY_CPU_CORTEX_M33&#160;&#160;&#160;(__CORTEX_M == 33U)</td>
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<p>The macro for ARM CORTEX CM33. </p>
<p>CM33 core CPU Code </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1c0ebfbdb81ba7c5a3601a4b274b7666">&#9670;&nbsp;</a></span>CY_ARM_FAULT_DEBUG</h2>

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          <td class="memname">#define CY_ARM_FAULT_DEBUG&#160;&#160;&#160;(<a class="el" href="group__group__syslib__macros.html#ga85e9d9dff858ec3d8dc503e008d73ee9">CY_ARM_FAULT_DEBUG_ENABLED</a>)</td>
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<p>The macro defines if the Fault Handler is enabled. </p>
<p>Enabled by default. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga42db4418238e39bcfd002d19df2587f5">&#9670;&nbsp;</a></span>CY_SYSLIB_DELAY_CALIBRATION_FACTOR</h2>

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          <td class="memname">#define CY_SYSLIB_DELAY_CALIBRATION_FACTOR&#160;&#160;&#160;1U</td>
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<p>This macro is to be enabled and set appropriately for the CPU's which has branch prediction enabled, so the delay can work accurately. </p>
<p>CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4. CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2b993962501511509b8b00983f63a3db">&#9670;&nbsp;</a></span>CY_SECTION_SHAREDMEM</h2>

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          <td class="memname">#define CY_SECTION_SHAREDMEM&#160;&#160;&#160;CY_SECTION(&quot;.cy_sharedmem&quot;)</td>
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<p>Define variable to be placed to the shared SRAM area by the linker. </p>
<p>This memory region is un-cached for CM55 core </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1587da210f7941e4b2fa119aa760d39b">&#9670;&nbsp;</a></span>CY_SECTION_SOCMEMSRAMDATA_BEGIN</h2>

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          <td class="memname">#define CY_SECTION_SOCMEMSRAMDATA_BEGIN&#160;&#160;&#160;CY_SECTION(&quot;.cy_socmem_data&quot;)</td>
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<p>Define end of code placed to the SOCMEMSRAM area by the linker. </p>
<p>Define start of data to be placed to the SOCMEMSRAM area by the linker </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa768a043f67cc8909f97862a2b221813">&#9670;&nbsp;</a></span>CY_SECTION_SOCMEMSRAMSHARED_BEGIN</h2>

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          <td class="memname">#define CY_SECTION_SOCMEMSRAMSHARED_BEGIN&#160;&#160;&#160;CY_SECTION(&quot;.cy_shared_socmem&quot;)</td>
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<p>Define end of code placed to the SOCMEMSRAM area by the linker. </p>
<p>Define start of shared data to be placed to the SOCMEMSRAM area by the linker. This memory region is un-cached for CM55 core </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac4b6fb05dfeabea3867f3de020c7f2b4">&#9670;&nbsp;</a></span>CY_SECTION_SRAM0DATA_BEGIN</h2>

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          <td class="memname">#define CY_SECTION_SRAM0DATA_BEGIN&#160;&#160;&#160;CY_SECTION(&quot;.cy_sram0_data&quot;)</td>
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<p>Define end of shared data to be placed to the SOCMEMSRAM area by the linker. </p>
<p>Define start of function placed to the bootstrap area by the linker Define end of function placed to the bootstrap area by the linker Placed initialized global variable to the bootstrap data area by the linker Placed un-init global variable to the bootstrap bss area by the linker Define start of the data placed in the SRAM0 area by the linker </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga340c178dff79aaf98298cb40037cf808">&#9670;&nbsp;</a></span>CY_UNUSED_PARAM</h2>

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          <td class="memname">#define CY_UNUSED_PARAM</td>
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          <td class="paramname">a</td><td>)</td>
          <td>&#160;&#160;&#160;(void)(a)</td>
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<p>Suppresses the unused parameter warning. </p>
<dl class="section note"><dt>Note</dt><dd>This macro is available for devices having M33SYSCPUSS IP. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5f6cdb90cc67d703db8007cd2b87633a">&#9670;&nbsp;</a></span>CY_ARRAY_SIZE</h2>

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          <td class="memname">#define CY_ARRAY_SIZE</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">x</td><td>)</td>
          <td>&#160;&#160;&#160;(sizeof(x) / sizeof((x)[0]))</td>
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<p>Returns the size of Array. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">x</td><td>Array Name</td></tr>
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  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This macro is available for devices having M33SYSCPUSS IP. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga16efc8820d2ece85d8dee3aed3198b6f">&#9670;&nbsp;</a></span>CY_IPC_DATA_FOR_CM4_SOFT_RESET</h2>

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          <td class="memname">#define CY_IPC_DATA_FOR_CM4_SOFT_RESET&#160;&#160;&#160;(0x1B000002UL)</td>
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<p>Bit[31:24] Opcode = 0x1B (SoftReset) Bit[7:1] Type = 1 (Only CM4 reset) </p>
<dl class="section note"><dt>Note</dt><dd>This macro is available for devices having M4CPUSS IP. </dd></dl>

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